It is well known that extremely high voltages can develop in the vicinity of an integrated circuit due to the build-up of static charge. A high potential may be generated to an input or output buffer of an integrated circuit, which may be caused by a person simply touching a package pin. When the electrostatic energy is discharged, a high current is produced through devices of the integrated circuit. Electrostatic discharge (ESD) is a serious problem for semiconductor devices, since it has the potential to destroy the device and the entire integrated circuit.
ESD protection devices are generally integrated into integrated circuits. An ESD protection device can provide a current path so that when an ESD transient occurs, the ESD current is conducted through the ESD protection device without going through the devices to be protected. High-voltage N-type metal-oxide-semiconductor (HVNMOS) devices are conventionally used as ESD protection devices, particularly for protecting high voltage semiconductor devices. FIG. 1 illustrates a conventional HVNMOS 2 that is used for ESD protection. The HVNMOS 2 includes a gate electrode 10, a gate dielectric 12, a drain region 4 in a high voltage N-well (HVNW) 16, and a source region 6 in a high voltage P-well (HVPW) 14. A shallow trench isolation (STI) region 8 isolates the drain region 4 and the gate electrode 10 so that high drain-gate voltage can be applied.
When used for ESD protection, the source region 6 is typically coupled to a power supply VSS, which is typically grounded, and the drain region 4 is coupled to an integrated circuit to be protected. If an electrostatic transient occurs and a reference voltage Vref at the drain region 4 increases, the HVNMOS 2 is turned on and the ESD current flows from the drain region 4 to the source region 6, so that the integrated circuit coupled to the drain region 4 is protected.
The ESD protection device formed by a HVNMOS 2 suffers drawbacks, however. The gate dielectric 12 traps charges when ESD occurs. Since HVNMOS transistors are commonly used under high operational voltage, the resulting high electric field leads to the incurrence of hot electrons around the junction of the channel and drain region. These hot electrons affect covalent electrons around the drain region by producing electron-hole pairs through the lifting of the electrons around the drain to conductive bands. When electrons travel between drain region 4 and source region 6, a small portion of the electrons are injected into and become trapped in the gate dielectric 12. Trapped charges cause the gate dielectric 12 to degrade. As a result, the HVNMOS's leakage current increases and breakdown voltage decreases. The HVNMOS may eventually fail when the maximum voltage it can sustain is lower than the electrostatic voltages.